RTL Power Estimation for Large Designs
نویسنده
چکیده
The increasing demand for portable electronic devices has led to emphasis on power consumption within the semiconductor industry. As a result, chip designers are now forced to consider the impact of not only speed and area, but also power throughout the entire design process. Power reduction has to be addressed at every design level, like system, RTL, gate and transistor-level where most power can be saved at the highest level. Good power estimation is essential for successful low power design. In order to evaluate how well a particular design type meets power constraints, designers have to often rely on CAD tools for power estimation. While tools have long existed for analyzing power consumption at the lower levels of abstraction like gate level and circuit level (PowerMill and SPICE) only recently tools with high-level power estimation capability are being developed. While system-level power estimation is new, power estimation from RTL-level and down have had many years to develop and mature. The RTL-power estimation can be divided into statisticaland simulation-based estimation. This paper surveys the various methods in high level power esimation, addressing techniques that operate at the RT Level of abstraction. Index Terms :Low power, gate level estimation, CAD tools, statistical analysis, RTL power estimation, analytical methods
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